FJV3101R ? npn epitaxial silico n transistor with bias resistor ? 2002 fairchild semiconductor corporation www.fairchildsemi.com FJV3101R rev. 1.1.2 1 november 2013 FJV3101R npn epitaxial silicon transistor with bias resistor features ? 100 ma output current capability ? built-in bias resistor (r 1 = 4.7 k , r 2 = 4.7 k ) application ? switching, interface, and driver circuits ? inverters ? digital applications in industrial segments ordering information absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. values are at t a = 25c unless otherwise noted. part number top mark package packing method FJV3101Rmtf r21 sot-23 3l tape and reel symbol parameter value unit v cbo collector-base voltage 50 v v ceo collector-emitter voltage 50 v v ebo emitter-base voltage 10 v i c collector current 100 ma t j junction temperature 150 c t stg storage temperature -55 to 150 c sot-23 1. base 2. emitter 3. collector 1 2 3 equivalent circuit c r1 e b r2 description transistors with built-in resistors can be excellent space- and cost-saving solutions by reducing compo- nent count and simplifying circuit design.
FJV3101R ? npn epitaxial silico n transistor with bias resistor ? 2002 fairchild semiconductor corporation www.fairchildsemi.com FJV3101R rev. 1.1.2 2 thermal characteristics (1) values are at t a = 25c unless otherwise noted. note: 1. fr-4 76 x 114 x 0.6t mm 3 (3.0 inch x 4.5 inch x 0.062 inch) with minimum land pattern size. electrical characteristics values are at t a = 25c unless otherwise noted. symbol parameter value unit p d power dissipation 200 mw derate above t a = 25c 1.60 mw/c r ja thermal resistance, junction to ambient 625 c/w symbol parameter conditions min. typ. max. unit bv cbo collector-base breakdown voltage i c = 10 a, i e = 0 50 v bv ceo collector-emitter breakdown voltage i c = 100 a, i b = 0 50 v i cbo collector cut-off current v cb = 40 v, i e = 0 0.1 a h fe dc current gain v ce = 5 v, i c = 10 ma 20 v ce (sat) collector-emitter saturation voltage i c = 10 ma, i b = 0.5 ma 0.3 v f t current gain bandwidth product v ce = 10 v, i c = 5 ma 250 mhz c ob output capacitance v cb = 10 v, i e = 0, f = 1.0 mhz 3.7 pf v i (off) input-off voltage v ce = 5 v, i c = 100 a0.5v v i (on) input-on voltage v ce = 0.3 v, i c = 20 ma 3 v r 1 input resistor 3.2 4.7 6.2 k r 1 /r 2 resistor ratio 0.9 1.0 1.1
FJV3101R ? npn epitaxial silico n transistor with bias resistor ? 2002 fairchild semiconductor corporation www.fairchildsemi.com FJV3101R rev. 1.1.2 3 typical performance characteristics figure 1. dc current gain figure 2. input-on voltage figure 3. input-off voltage figure 4. power derating 1 10 100 1000 10 100 1000 v ce = 5v r 1 = 4.7k r 2 = 4.7k h fe , dc current gain i c [ma], collector current 0.1 1 10 100 0.1 1 10 100 v ce =0.3v r 1 = 4.7k r 2 = 4.7k v i (on)[v], input voltage i c [ma], collector current 0.0 0.4 0.8 1.2 1.6 2.0 2.4 10 100 1000 v ce = 5v r 1 = 4.7k r 2 = 4.7k i c [ a], collector current v i (off)[v], input off voltage 0 25 50 75 100 125 150 175 0 40 80 120 160 200 240 280 p c [mw], power dissipation t a [ o c], ambient temperature
FJV3101R ? npn epitaxial silico n transistor with bias resistor ? 2002 fairchild semiconductor corporation www.fairchildsemi.com FJV3101R rev. 1.1.2 4 physical dimensions figure 5. 3-lead, sot-23, jedec to-236, low profile (active) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/ma/ma03d.pdf . for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/p acking_dwg/pkg-ma03d_bk.pdf . land pattern recommendation notes: unless otherwise specified a) reference jedec registration to-236, variation ab, issue h. b) all dimensions are in millimeters. c) dimensions are inclusive of burrs, mold flash and tie bar extrusions. d) dimensioning and tolerancing per asme y14.5m - 1994. e) drawing file name: ma03drev10 3 12 see detail a seating plane scale: 2x gage plane (0.55) (0.93) 1.20 max c 0.10 0.00 0.10 c 2.400.30 2.920.20 1.30 +0.20 -0.15 0.60 0.37 0.20 a b 1.90 0.95 (0.29) 0.95 1.40 2.20 1.00 1.90 0.25 0.23 0.08 0.20 min sot-23
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